1. Field of the Invention
The invention relates generally to a method of manufacturing semiconductor devices, and more particularly to a method of manufacturing a flash cell and a transistor in a peripheral circuit.
2. Description of the Prior Art
Semiconductor device are mainly divided into RAM products such as DRAM (dynamic random access memory) and SRAM (static random access memory) wherein data therein is lost as the time passes, which are volatile and fast in the input/output of the data, and ROM (read only memory) products which can maintain the data if the data is once inputted but is low in input/output of the data.
These ROM products may be classified into ROM, PROM (programmable ROM), EPROM (erasable PROM) and EEPROM (electrically EPROM). Among them, there is a trend that EEPROM capable of programming and erasing the data by an electrical method is increasingly demanded. The EEPROM or the flash EEPROM having a batch erasure function has a stack-type structure in which a floating gate electrode and a control gate electrode are stacked.
A memory cell of a stack-type gate structure can program/erase the data by means of a F-N tunneling (Fowler-Nordheim tunneling) effect and has a structure in which a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode are stacked on a semiconductor substrate. A plurality of metal bit lines having a constant distance in a column direction, are positioned in a memory cell array consisting of a plurality of the memory cells. Pluralities of word lines are positioned in a direction orthogonal to the plurality of the metal bit lines. Also, a single common source line is positioned every two word lines in the memory cell array. The common source line is positioned in the same direction to the word lines and consists of a plurality of common source junctions and a source connection layer. The metal bit lines are connected to the drain junctions via a metal contact formed between the two gate electrodes.
The method of manufacturing the flash cell array will be explained in detail as follows.
A device isolation film is formed on a semiconductor substrate, through isolation process such as local oxidation of silicon (LOCOS) process, thus defining an active region. A tunnel oxide film and a first polysilicon silicon layer for a floating gate electrode are sequentially formed on the active region of the semiconductor substrate. Then, the first polysilicon silicon layer on the field oxide film is etched by a photolithography process to separate the floating gate electrodes of each of the cells in a bit line direction. Thereafter, an ONO (oxide/nitride/oxide) film as a dielectric film, a second polysilicon layer and an insulating film for a control gate electrode (for use in a hard mask layer or an anti-reflection film) are sequentially stacked on the entire structure. Then, after forming a photoresist pattern for forming the word lines on the insulating film, the insulating film, the second polysilicon layer, the dielectric film and the first polysilicon silicon layer are sequentially etched using the photoresist pattern as an etch mask to form a stack type gate structure. At this time, the gate electrodes are formed in the peripheral circuit region.
Thereafter, the photoresist pattern is formed to open a region in which the common source region will be formed by means of photolithography process in order to perform a self align source (SAS) etching process. Next, the device isolation film in the opened regions is etched using the photoresist pattern as an etch mask. In order to form a spacer while compensating for a portion damaged by the self align source etch process, a self align source annealing process is performed. Then, a source/drain ion implantation process is performed to form a source and drain junction in the cell region and a low concentration junction in the peripheral circuit region. The oxide film for a spacer is deposited on the entire structure and the spacer is then formed by means of a blanket etch process being a subsequent process. Thereafter, a high concentration junction is formed in the peripheral circuit region for driving the cells by a high concentration ion implantation process, thus completing a transistor.
Next, a high temperature oxide (HTO) film, a PSG film and a borophosphosilicate glass (BPSG) film are sequentially deposited on the entire structure and the BPSG film is then flattened by a re-flow process in order to protect and flatten the cells and the transistor. Then, the layers stacked on the drain region of the cells via the photolithography process are removed by means of wet etch and dry etch to form a metal contact. Thereafter, a metal layer is deposited on the resulting surface and is then pattern by means of the photolithography process, thus forming bit lines electrically connected to the drain regions of the cells via the bit line contact.
The method of manufacturing the flash cell array has the following problems.
First, loss in the source junction of the semiconductor substrate, which is generated by the self align source etch process, is not uniform every portions. Thus, there is a difference in the overlapping range between the floating gate electrode and the source junction every loss portions. As a result, there occurs a problem that the characteristics of the cells constituting the array are not same.
Second, there is a problem that a locally bird""s beak phenomenon the thickness of the oxide films constituting the ONO structure at the edge region of the dielectric film in the ONO structure is increased by means of the self align source annealing process, which is performed in order to compensate for damaged portions after the self align source etch process, is generated. As the thickness of the oxide films forming the ONO structure every cells is different by means of the above problem, a coupling ratio between the junctions of each of the cells and the floating gate electrode is different. Due to this, there occurs a difference in an electric field every cells. Thus, there is a difference in the erase operating speed in the cells within the sector using a F-N tunneling method, which degrades the erase distribution of the cells.
Third, there are problem that the tungsten silicide (WSi) film constituting the control gate electrode is opened upon the self align source etch process and the spacer is thickly formed at the opened tungsten silicide (WSi) film by the self align source annealing process being a subsequent process. This results from that the oxidation rate of the tungsten silicide (WSi) is very slow, which causes fluorine to leak from the tungsten silicide (WSi) film upon deposition a CVD spacer oxide film being a subsequent process so that the coupling between silicon (Si) and fluorine (F) rather than the coupling between silicon (Si) and oxygen (O) is prioritized. Due to this, the deposition speed of the spacer is locally increased to generate defects in the spacer and the width of the spacer is locally changed by the defects to cause a non-uniformity of a transistor characteristic.
Fourth, there occurs a non-uniformity of the source and drain junction depth, that is formed in a transistor of the peripheral circuit region. This problem is generated because the high concentration ion implantation process performed after the spacer etch process employs an oxide film remaining on the surface as a screen oxide film, employs a source material having a high atomic amount such as arsenic in order to prohibit the side diffusion and uses a low energy as an ion implantation energy. That is, the problem of the non-uniformity in the source and drain junction depth heavily depends on the uniformity of the oxide film remaining on the surface upon ion implantation process. In a prior art, as the deposited oxide film is experienced by a blanket etch process to etch the oxide film, it is difficult to obtain an oxide film having an uniform thickness and variations in the sheet resistance value of the junction used as the transistor characteristic and the passive device becomes also large.
Fifth, there is a problem of a short that occurs between the gate electrode and the junction. If the gate electrode and the junction being independent terminals contact, an unnecessary leakage current flows. This problem easily causes a short between the gate electrode and the junction by means of mis-alignment and pre-metal cleaning as the size of the transistor becomes smaller so the distance between the gate electrode and the junction becomes reduced.
Therefore, there is a need for a new method of manufacturing a flash cell for solving the above problems.
It is therefore an object of the present invention to increase the integrity capability of data by sequentially forming a dichlorosilane (DCS; SiH2Cl2) HTO film and a nitride film on the entire surface after a self align source etch process to prevent a local bird""s beak phenomenon of a dielectric film between the floating gate electrode and a control gate electrode and using a spacer for compensating for the sidewall of a gate structure damaged upon the self align source etch process to prevent a movement of charges and holes between a floating gate electrode and a peripheral portion.
Also, another object of the present invention is to protect the gate electrodes from a stress applied by a subsequent process and also prevent generation of an oxide film generated by the subsequent process, by sequentially forming the DCS HTO and the nitride film on the entire structure.
In addition, a still another object of the present invention is to make uniform the depth of a junction upon a high concentration ion implantation and to improve the characteristic of transistors in a peripheral circuit and the uniformity of a diffusion resistance value, by allowing the nitride film to serve as a stopper by a select ratio upon the DCS HTO film etching process for forming a screen oxide film so that the etching rate can be controlled by sequentially forming the DCS HTO film and the nitride film on the entire structure.
In order to accomplish the above object, a method of manufacturing a semiconductor device according to the present invention is characterized in that it comprises the steps of providing a semiconductor substrate in which a cell region and a peripheral circuit region are defined; forming a patterned tunnel oxide film, a floating gate electrode and a control gate electrode in said cell region forming a gate electrode in said peripheral circuit region; removing an exposed portion of a device isolation film in said cell region by means of a self align source etch process; forming a first capping layer and a second capping layer on the entire structure; performing a self align source annealing process for said cell region; forming a source and drain junction in said cell region and forming a low concentration source and drain junction in said peripheral circuit region; forming a gate spacer in said peripheral circuit region; and forming a high concentration source and drain junction in said peripheral circuit region.